The present invention relates generally to the field of microprocessors for use in computer systems; more particularly, to apparatus and methods used to control the timing of data operations in a high-performance processor.
Very large integrated circuits often synchronize data operations to a clocking signal that acts as a global timing reference. A great variety of circuit devices operate in this manner. Perhaps most notable of these circuits are microprocessors and other data processing devices which can operate at high frequencies.
In such circuits there is a need to couple the clocking signal to each of the functional blocks distributed about the semiconductor chip. This means that integrated circuits operating synchronously, such as a microprocessor, have a need for a network that distributes the clock signal across the chip. In a typical microprocessor, for example, the clock signal is often generated internal to the chip from an external signal that provides a reference frequency input. The external clock signal is commonly derived from a crystal resonator circuit. The internally generated clock signal is then coupled to the various functional units or logic clusters of the microprocessor. Synchronous logic functions obviously imply the need for some sort of clock distribution network.
The prior art includes numerous examples of different clock generator circuit designs coupled with distribution networks designed to achieve a global clocking signal having a low clock skew across a large chip. For example, U.S. Pat. Nos. 5,289,866; 5,307,381; 5,339,253; 5,361,277; 5,376,842; 5,397,943; and 5,398,262 describe clock distribution networks and clock synchronization circuitry for use in a very large scale integrated circuit such as microprocessor.
Communication of data from one agent into another agent in a computing system is commonly achieved in accordance with a source synchronous protocol. The source synchronous protocol involves sending data along with a clock signal or strobe from a transmitting agent to a receiving agent. The receiving agent then uses the clock signal to synchronously latch or save the received data. Typically, the receiving element derives its latching signal from the incoming strobe. One prior art method is to have the strobe or clock signal related to the data such that if the data it is sent on a rising clock edge, the strobe signal edge transition occurs at the center of the changing data. This is called centered source synchronous strobing.
Because logic operations in a processor are also tied to the processor""s global system clock, it is important that input/output (I/O) clock generation be synchronized with the global system clock signal. Commonly, however, the input/output (I/O) devices that rely upon I/O clock signals require that the I/O clock signal be at a frequency less than the frequency of the core system clock. For example, the frequency of bus operations are often fixed to a reference clock signal. The core frequency of the processor is often a much higher rate than the reference clock frequency associated with the bus. By way of example, some advanced processors can operate with a core frequency greater than 500 MHz. Within that range, there is a need to support the fixed data rate transactions that occur on the bus.
One problem that exists is that the global clocking signal (i.e., associated with the core frequency) and the bus clock signal ratio is such that the I/O clock signal cannot be generated directly from the global (core) clocking signal. Moreover, if they are not generated locally, extensive routing of I/O clock signals in a chip takes a valuable space and power and can introduce delays and other inaccuracies in the clock signal.
Thus, there exists a need for a method and apparatus that generates I/O clock signals used for data transfers that is derived from the global system clock, without requiring additional routing of clock signals. Furthermore, the data transfer rate should be consistent regardless of varying or unusual core/bus clock frequency ratios.
Various apparatuses and methods to generate a clock signal that controls data operations in an integrated circuit. In an embodiment, a circuit for generating a clock signal that controls data operations in an integrated circuit includes a first clock synthesizer, a divider circuit, and a second clock synthesizer. The first clock synthesizer produces a first signal derived from an external reference signal. The first signal has a first frequency that is greater than a frequency of the external reference signal. The divider circuit divides the frequency of the first signal by N, where N is an integer greater than 1. The divider circuit outputs a second signal having a second frequency which is equal to the first frequency divided by N. The second clock synthesizer couples to the divider circuit for producing the clock signal at a frequency which is an integer multiple of the second signal. The second clock synthesizer also produces a strobe signal. The strobe signal has a rising edge that is either centered, or is coincident, with respect to a changing data signal of a processor.